1 features ? ? one diferential lvpecl output ? ? crystal oscillator interface, 18pf parallel resonant crystal (23.2mhz - 30mhz) ? ? output frequency range: 290mhz - 750mhz ? ? rms phase jitter @ 312.5mhz, using a 25mhz crystal (12khz - 20mhz): 0.3ps (typical), 0.5ps (max) ? ? 3.3v or 2.5v operating supply ? ? -40c to 85c operating temperature ? ? available in 8pin tssop pi6lc48p0101 block diagram pin confguration description te pi6lc48p0101 is a 10gb ethernet clock generator. te pi6lc48p0101 uses an 18pf parallel resonant crystal over the range of 23.2mhz - 30mhz. for ethernet applications, a 25mhz crystal is used. te pi6lc48p0101 can achieve <0.5ps rms phase jitter performance over the 12khz - 20mhz integration range. te pi6lc48p0101 is packaged in a small 8-pin tssop, making it ideal for use in systems with limited board space. hiflex 10gbe clock generator 1 2 3 4 5 v dda 6 7 8 xtal_in/ ref_in v dd v ee q- freq_sel xtal_out q+ xtal_in/ ref_in xtal_out osc q+ q- pulldown m = : 25 (fixed) phase detector vco freq_sel n 1 : 1 0 (default) : 2 freq_sel common confguration table inputs output frequency (mhz) crystal frequency (mhz) freq_sel m n multiplication value m/n 25 1 25 1 25 625 25 0 25 2 12.5 312.5 www.pericom.com pi6lc48p0101 rev a 09/01/15 15-0117
2 pin # pin name ty pe description 1 v dda power analog supply pin. 2 v ee power negative supply pin. 3 xtal_out output xtal_out is the output. 4 xtal_in/ ref_in input xtal_in, can also be driven by a single ended reference clock 5 freq_sel input pulldown frequency select pin. lvcmos/lvttl interface levels. 6, 7 q-, q+ output diferential clock outputs. lvpecl interface levels. 8 v dd power core supply pin. note: pulldown refers to internal input resistors. see pin characteristics for typical values. pin description pin characteristics symbol parameter test condition minimum ty pica l maximum units c in input capacitance 4 pf r pulldown input pulldown resistor 51 k pi6lc48p0101 hiflex 10gbe clock generator www.pericom.com pi6lc48p0101 rev a 09/01/15 15-0117
3 maximum ratings note: note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. tese ratings are stress specifcations only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may afect product reliability. lvcmos/lvttl dc characteristics (v dd = 3.3v5% or 2.5v5%, v ee = 0v, t a = -40c to 85c) symbol parameter test condition min. ty p. max. units v ih input high voltage v dd = 3.3v 2 v dd + 0.3 v v dd = 2.5v 1.7 v dd + 0.3 v v il input low voltage v dd = 3.3v -0.3 0.8 v v dd = 2.5v -0.3 0.7 v i ih input high current v dd = v in = 2.625v or 3.465v 150 a i il input low current v dd = 2.625v or 3.465v, v in = 0v -5 a dc electrical characteristics power supply dc characteristics (v dd = 3.3v5%, v ee = 0v, t a = -40c to 85c) symbol parameter test condition min. ty p. max. units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage v dd C 0.25 3.3 v dd v i ee power supply current 83 ma i dda analog supply current 28 ma power supply dc characteristics (v dd = 2.5v5%, v ee = 0v, t a = -40c to 85c) symbol parameter test condition min. ty p. max. units v dd core supply voltage 2.375 2.5 2.625 v v dda analog supply voltage v dd C 0.25 2.5 v dd v i ee power supply current 78 ma i dda analog supply current 28 ma storage temperature .............................................. -65oc to+155oc temperature with power applied ......................... -40oc to+85oc 3.3v supply voltage .................................................... -0.5 to +3.6v esd protection (hbm) ......................................................... 2000v pi6lc48p0101 hiflex 10gbe clock generator www.pericom.com pi6lc48p0101 rev a 09/01/15 15-0117
4 lvpecl dc characteristics ( v dd = 3.3v5%, v ee = 0v, t a = -40c to 85c) symbol parameter test condition min. ty p. max. units v oh output high voltage* v dd = 3.3v 1.9 2.4 v v dd = 2.5v 1.1 1.6 v ol output low voltage* v dd = 3.3v 1.2 1.6 v v dd = 2.5v 0.4 0.8 v swing peak-to-peak output voltage swing 0.6 1.0 v note: lvpecl termination: source 150ohm to gnd and 100ohm across clk+ and clk- crystal characteristics parameter test condition min. ty p. max. units mode of oscillation fundamental frequency 23.2 30 mhz equivalent series resistance (esr) 40 shunt capacitance 7 pf note: it is not recommended to overdrive the crystal input with an external clock. pi6lc48p0101 hiflex 10gbe clock generator www.pericom.com pi6lc48p0101 rev a 09/01/15 15-0117
5 ac electrical characteristics (v dd = 3.3v5%, v ee = 0v, t a = -40c to 85c) symbol parameter test conditions min. ty p. max. units f out output frequency freq_sel = 0 312.5 mhz freq_sel = 1 625 mhz tjit rms phase jitter (random)* 312.5mhz @ integration range: 12khz - 20mhz 0.3 0.5 ps 312.5mhz @ integration range: 1.875mhz - 20mhz 0.1 625mhz @ integration range: 12khz - 20mhz 0.3 0.5 ps 625mhz @ integration range: 1.875mhz - 20mhz 0.07 t r / t f output rise/fall time 20% to 80% 100 400 ps odc output duty cycle 47 53 % note: refer to the phase noise plots following this section. ac electrical characteristics (v dd = 2.5v5%, v ee = 0v, t a = -40c to 85c) symbol parameter test conditions min. ty p. max. units f out output frequency freq_sel = 0 312.5 mhz freq_sel = 1 625 mhz tjit rms phase jitter (random)* 312.5mhz @ integration range: 12khz - 20mhz 0.3 0.5 ps 312.5mhz @ integration range: 1.875mhz - 20mhz 0.1 625mhz @ integration range: 12khz - 20mhz 0.3 0.5 ps 625mhz @ integration range: 1.875mhz - 20mhz 0.07 t r / t f output rise/fall time 20% to 80% 100 400 ps odc output duty cycle 47 53 % note: refer to the phase noise plots following this section. pi6lc48p0101 hiflex 10gbe clock generator www.pericom.com pi6lc48p0101 rev a 09/01/15 15-0117
6 phase noise plots 312.5mhz 625mhz pi6lc48p0101 hiflex 10gbe clock generator www.pericom.com pi6lc48p0101 rev a 09/01/15 15-0117
7 50 150 0.01f z = 50 l = 0 ~ 10in 150 device o z = 50 o 50 0.01f lvpecl test circuit power supply filtering techniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perfor - mance, power supply isolation is required. te pi6lc48p0101 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd and v dda should be individually connected to the power supply plane through vias, and 0.1f bypass capacitors should be used for each pin. figure below illustrates this for a generic v dd pin and also shows that v dda requires that an additional 10 resistor along with a 10f bypass capacitor be connected to the v dda pin. v dd 0.1f 0.1f 10f 10? * 3.3v or 2.5v v dda * if v dd is 2.5v, the resistor value will be di erent, see app note for details pi6lc48p0101 hiflex 10gbe clock generator www.pericom.com pi6lc48p0101 rev a 09/01/15 15-0117
8 crystal input interface te clock generator has been characterized with 18pf parallel resonant crystals. te capacitor values shown in the fgure below were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. c1 27pf c2 27pf xtal_in xtal_out x1 18pf parallel crystal lvcmos to xtal interface te xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in the fgure below. te xtal_out pin can be lef foating. te input edge rate can be as slow as 10ns. for lvcmos signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. tis confguration requires that the output impedance of the driver (ro) plus the series resis - tance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. tis can be done in one of the two ways. first, r1 and r2 in parallel should equal the transmission line empedance. for most 50 applications, r1 and r2 can be 100 . this can also be accomplished by removing r1 and making r2 50. by overdriving the crystal oscillator, the device will be functional, but note, the device performance is quaranteed by using a quartz crystal. v r2 50 dd ro rs zo = ro + rs r1 xtal_in xtal_out v dd 0.1f thermal information symbol description q ja junction-to-ambient thermal resistance 124 o c/w q jc junction-to-case thermal resistance 37 o c/w pi6lc48p0101 hiflex 10gbe clock generator www.pericom.com pi6lc48p0101 rev a 09/01/15 15-0117
9 date: 05/03/12 description: 8 pin, 173mil wide tssop package code: l document control #: pd-1308 revision: f notes: 1. refer jedec mo-153f/aa 2. controlling dimensions in millimeters 3. package outline exclusive of mold flash and metal burr 12-0370 packaging mechanical: ordering code package code pack age ty pe PI6LC48P0101LIE l pb-free & green, 8-pin tssop PI6LC48P0101LIEx l pb-free & green, 8-pin tssop, tape & reel notes: 1. termal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. e denotes pb-free and green 3. adding an x at the end of the ordering code denotes tape and reel packaging ordering information pi6lc48p0101 hiflex 10gbe clock generator www.pericom.com pi6lc48p0101 rev a 09/01/15 15-0117
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